FAN9611MX【PDF 12/35 页】IC PFC CTLR DUAL BCM 16-SOIC

?2008 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FAN9611 " Rev. 1.1.7

12

This method is especially dangerous in power-factor-

corrector applications because the error amplifiers

bandwidth is typically limited to a very low crossover

frequency. The slow response of the amplifier can

cause considerable overshoot at the output.

FAN9611 employs closed-loop soft-start where the

reference voltage of the error amplifier is slowly

increased to its final value. When the current and power

limits of the converter are properly taken into

consideration, the output voltage of the converter

follows the reference voltage. This ensures that the

error amplifier stays in regulation during soft start and

the output voltage overshoot can be eliminated.

Functional Description

1. Detecting Zero Inductor Current

(ZCD1, ZCD2)

Each ZCD pin is internally clamped close to 0 V (GND).

Any capacitance on the pin is ineffective in providing

any delay in ZCD triggering. The internal sense circuit is

a true differentiator to catch the valley of the drain

waveforms. The resistor between the auxiliary winding

of the boost inductor and the ZCD pin is only used for

current limiting. The maximum source current during

zero current detection must be limited to 0.5 mA. If the

sourcing current is larger than 0.5 mA, the internal

detection circuit is saturated and the ZCD circuit can be

prematurely triggered before reaching the actual ZCD

valley threshold. Source and sink capability of the pin

are about 1 mA and 10 mA, respectively. The stronger

sinking current capability provides sufficient margin for

the higher sinking current required during the

conduction time of the rectifier diode.

Figure 16. Zero-Current Detect Circuit

The R

ZCD

resistor value can be approximated by:

BOOST

AUX

O

ZCD

N

V

mA

.

R

?/DIV>

=

2

5

0

1

(1)

2. 5 V Bias Rail (5VB)

This is the bypass capacitor pin for the internal 5 V bias

rail powering the control circuitry. The recommended

capacitor value is 220 nF. At least a 100 nF, good-

quality, high-frequency, ceramic capacitor should be

placed in close proximity to the pin.

The 5 V rail is a switched rail. It is actively held LOW

when the FAN9611 is in under-voltage lockout. Once

the UVLO turn-on threshold is exceeded at the VDD pin,

the 5 V rail is turned on, providing a sharp edge that can

be used as an indication that the chip is running.

Potentially, this behavior can be utilized to control the

inrush current limiting circuit.

Figure 17. 5V Bias

3. Maximum On-Time Control (MOT)

Maximum on-time, MOT, (of the boost MOSFET) is set

by a resistor to analog ground (AGND). The FAN9611

implements input-voltage feedforward. The maximum

on-time is a function of the RMS input voltage. The

voltage on the MOT pin is 1.25 V during operation

(constant DC voltage). The maximum on-time of the

power MOSFETs can be approximated by:

12

,

2

,

2.4

1

120 10

1.25

ON MAX

MOT

INSNS PK

t

R

V

=

?nbsp ?/DIV>

?/DIV>

(2)

where V

INSNS,PK

is the peak of the AC input voltage as

measured at the VIN pin (must be divided down, see

the VIN pin description).

Figure 18. Maximum On-Time Control (MOT)

External

Components

Internal

Circuits

1 (2)

ZCD

Positive

Clamp

Negative

Clamp

0.3/0.0V

.

R ZCD

To ZCD

winding

To arm ZCD

detecto

ZCD Valle

Detector

ZCD

signal

(true differentiato)

PWM

signal

ARM

(ready

)

INHIBIT

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